A pseudo static random access memory (PSRAM) has been developed recently, and the demand for PSRAMs is becoming extensive. A PSRAM uses as its memory cell a dynamic type memory cell constructed of one transistor and one capacitor used in a dynamic random access memory (DRAM), and uses as its peripheral circuit a peripheral circuit used in a static random access memory (SRAM). By virtue of such a circuit arrangement, a PSRAM has both the characteristics of DRAMs and SRAMs, i.e., the low cost and large capacity of a DRAM and the ease of use of a SRAM.
As described above, a PSRAM uses a dynamic memory cell the same as that of a DRAM. Therefore, a refresh operation is required to hold data stored in this memory cell. In order to facilitate refresh operation control, a memory device is provided with a refresh control terminal RFSH. By using a refresh signal, the PSRAMs now available on the market are refreshed while they are not being accessed.
In a computer system (PSRAM apparatus) as shown in FIG. 8, a PSRAM 1 is used for data read/write, and an instruction read from a ROM 2 is executed by a microprocessor unit MPU 3. In such a system, while an instruction is read from ROM 2, PSRAM 1 is not accessed for data read/write operation. Consequently, a refresh operation is performed while the instruction is read.
FIG. 9 shows an example of the operation of the system shown in FIG. 8. In this operation, MPU 3 executes an instruction read from ROM 2 (cycle I), a data read from PSRAM 1 (cycle II), an instruction read from ROM 2 (cycle III), and a data write to PSRAM 1 (cycle IV). In this case, a period longer than half the operation time is consumed for reading ROM 2. Therefore, if the instruction read cycles I and III are used as the refresh cycles of PSRAM 1, it is easy to refresh all the memory cells in a PSRAM within a certain period. FIGS. 9(b) to 9(e) show the level change of signals supplied from MPU 3 and a decoder 4 to the associated terminals of PSRAM 1 and ROM 2. Upon application of the signals having such level changes to the associated terminals, the above-described operations of MPU 3 and PSRAM 1 are carried out during the respective cycles I to IV. FIG. 9(b) and 9(c) show the signals supplied from the decoder 4 to CE terminals of ROM 2 and PSRAM 1. FIG. 9(d) shows the signal supplied from a RD terminal of MPU 3 to an OE/RFSH terminal of PSRAM 1 and to an OE terminal of ROM 2. FIG. 9(e) shows the signal supplied from a WR terminal of MPU 3 to a R/W terminal of PSRAM 1.
However, a refresh operation control as described above becomes practically impossible for a system in which a ROM is not used but instructions and data are stored in the common PSRAM, for sound systems for which the operating speed is slow, or for certain systems handling image information. In order to allow refresh operation control for such systems, the following various circuit elements are required: namely, a timer for supervising the timing when a refresh operation becomes necessary, an arbitrator circuit for determining the priority order for the case where a PSRAM refresh operation and an access operation conflict with each other, a circuit for causing the system to enter into a standby state during a refresh operation, and other circuits. The system accordingly becomes complicated, and the characteristics of low cost and facility of PSRAMs are hindered.